ESP 32 Development Board

Specifications

CPU: Xtensa dual-core 32-bit LX6 microprocessor, operating at 240 MHz and performing at up to 600 DMIPS
Ultra-low power (ULP) co-processor
Memory: 520 KiB SRAM
Wireless connectivity:
Wi-Fi: 802.11 b/g/n
Bluetooth: v4.2 BR/EDR and BLE (shares the radio with Wi-Fi)
Peripheral interfaces:
12-bit SAR ADC up to 18 channels
2 x 8-bit DACs
10 x touch sensors (capacitive sensing GPIOs)
4 x SPI
2 x I2S interfaces
2 x I2C interfaces
3 x UART
SD/SDIO/CE-ATA/MMC/eMMC host controller
SDIO/SPI slave controller
Ethernet MAC interface with dedicated DMA and IEEE 1588 Precision Time Protocol support
CAN bus 2.0
Infrared remote controller (TX/RX, up to 8 channels)
Motor PWM
LED PWM (up to 16 channels)
Hall effect sensor
Ultra-low-power analogue pre-amplifier
Security:
IEEE 802.11 standard security features are all supported, including WFA, WPA/WPA2 and WAPI
Secure boot
Flash encryption
1024-bit OTP, up to 768-bit for customers
Cryptographic hardware acceleration: AES, SHA-2, RSA, elliptic curve cryptography (ECC), random number generator (RNG)
Power management:
Internal low-dropout regulator
Individual power domain for RTC
5mA deep sleep current
Wake up from GPIO interrupt, timer, ADC measurements, capacitive touch sensor interrupt